The following criteria, which are substantially affected by the circuit technology of a read amplifier, can be considered in judging the quality of read-write circuits.
1. The speed of the reading process. It is to be noted that a small delay in a single access does not automatically entail a high data rate in other modes of operation, such as page mode or static column mode.
2. Current draw and space requirement are important especially when a plurality of read-write circuits are used; yet this is necessary due to the external organization (4-bit or 8-bit) but also due to the internal organization (block structure in the case of VLSI memories), or for making function testing effective in the so-called "test mode."
3. Limiting the level shift serves to reduce the power loss and to achieve a high speed, but it is important above all for the reduction of capacitative disturbances of the matrix.
For the reading out of information from the bit lines a variety of types of read amplifiers have been developed. In EP 130 910 there is described a read amplifier of the flip-flop type, in which two cross-coupled CMOS inverters, after a preset by a reference voltage, flip according to the signal on the data line. In that case, however, the data line is raised to the full voltage (U.sub.cc or U.sub.es). The flip of the flip-flop is undesirable since high voltages have to be dissipated, even if only reading is done. A short delay in reading is possible in such circuits only in the case of optimal data line bias. Consequently such circuits are unsuitable for the rapid read-out of the information from the cells of a line without changing the column address (static column mode).
EP 180 193 describes a read amplifier which is composed of a pair of cross-coupled CMOS Schmitt Triggers. It is disadvantageous in this case also that the output voltages lag behind the input voltages, which in the static column mode leads to losses of speed.
Another possibility is the use of difference amplifiers, some of them multi-stage amplifiers, which by operating in the linear range fulfill an important requirement for a high speed in the static column mode. For this purpose, however, a relatively high forward current is necessary during the entire read process. Furthermore, here too a complete reversal of the data lines occurs unless this is prevented by additional circuitry (clamping circuits).
The aim of the invention is to develop a fast read-write circuit which will assure reading at a high data rate in the static column mode while requiring a minimum amount of space and a very small level shift on the data lines, and in which the write circuit is partially integrated into the read circuit.